The interest in nanoscaled electronic devices has during the last decade increased substantially. The interest arises from the continuous need for denser integrated circuits, but also from the realization that nanoscale electronic devices offers new possibilities in terms of operational speed, functionality and power consumption, for example. These new possibilities, but also in some aspects new challenges, are primarily related to the exploration of quantum mechanical effects coming into importance as the size of devices go down to the nano-region. The scaling also allows for an materials integration that may not be achieved in the conventional technologies. Of particular interest are devices based on semiconductor nanowires. Semiconductor nanowires is in this context defined as rod-shaped structures with a diameter less than 200 nm and a length up to several μm. Semiconductor nanowires may be grown on different types of substrates and they can be arranged to grow vertically from the substrate. This enables a number of vertical device technologies, including diodes, transistors, and optical sources and detectors. The nanowire forms the main functional part in these various devices, for example the current channel of a transistor or the light emitting portion of optical source. Common to all such devices are that external electrodes must be formed to get electrical access to the nanowires. Typically nanowires have contacts of conductive material, for example metal, integrally formed with the semiconductor on their end parts. The electrodes include ohmic (i.e. non-rectifying) contacts to the ends of the nanowire and possibly one or several gate electrodes to the center region between the ohmic contacts. A nanowire device typically comprises a large plurality of nanowires in a parallel configuration. The simplest, and the most common way, to provide external contact to the nanowires is to provide sheets, or layers of conducting material on appropriate “heights” of the nanowire. This is exemplified by the transistor structure 100 of FIG. 1a, comprising of a plurality of nanowires 105 grown from a substrate 102, each nanowire 105 provided with a source contact, a gate contact and a drain contact. External connection to the contacts are arranged by providing external electrodes, which also can be referred to as external contacts, in the form of a source conducting layer 110, a gate conducting layer 115 and a drain conducting layer 120. The conducting layers can be seen as forming conducting sheets extending throughout the device at different heights from the substrate. The diameters of nanowires are typically below 200 nm and the spacing between the nanowires are in the same range, there will be a substantial geometrical overlap between the (external parts of the?) electrodes. Given that the operation of the devices requires a potential differences between the different gates this overlap will may cause substantial parasitic capacitances and increased leakage currents between the electrodes. These effects reduce the performance of the devices.
Lateral technologies, which today predominate in microelectronics, allows electrodes to be fabricated with limited overlay. In the lateral technology, the overlay is mainly determined by the thickness of the electrode, whereas the overlay in vertical technologies is mainly given by the line width of the lithography used. In the vertical nanowire technology, there will always, as described above, be a direct unavoidable overlay between the electrodes. In contrast, lateral technologies allow electrodes to be fabricated with limited overlay. In addition, as compared to established microelectronic technologies the above mentioned parasitic effects will be larger for the nanowire technology. For a given current density the ratio between the drive current and the parasitic capacitances will be smaller for the nanowires due to the smaller geometrical dimensions. Hence, the parasitic effects are more critical in the nanowire technology compared to established microelectronic technology.
In U.S. Pat. No. 6,314,019 a cross-bar geometry with molecular wires is described, wherein in the junctions simple electronic devices, for example switches, are formed in the interaction between the two wires. The technique is not readily applicable to more complex electronic devices.